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PD - 91818A
SMPS MOSFET
IRFBL12N50A
HEXFET(R) Power MOSFET
Applications l Switch Mode Power Supply (SMPS) l Uninterruptible Power Supply l High Speed Power Switching Benefits Low Gate Charge Qg Results in Simple Drive Requirement l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche Voltage and Current
l
VDSS
500V
RDS(on) max
0.45
ID
13A
Super-D2PakTM
Absolute Maximum Ratings
Parameter
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds
Max.
13 8.2 52 180 1.4 30 3.1 -55 to + 150 300 (1.6mm from case )
Units
A W W/C V V/ns C
Typical SMPS Topologies
l l
Active Clamped Forward Main Switch
Notes
through
are on page 8
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1
2/16/00
IRFBL12N50A
Static @ TJ = 25C (unless otherwise specified)
V(BR)DSS RDS(on) VGS(th) IDSS IGSS Parameter Drain-to-Source Breakdown Voltage Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Min. 500 --- 2.0 --- --- --- --- Typ. --- --- --- --- --- --- --- Max. Units Conditions --- V VGS = 0V, ID = 250A 0.45 VGS = 10V, ID = 7.8A 4.0 V VDS = VGS , ID = 250A 25 VDS = 500V, VGS = 0V A 250 VDS = 400V, VGS = 0V, TJ = 150C 100 VGS = 30V nA -100 VGS = -30V
Dynamic @ TJ = 25C (unless otherwise specified)
gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Coss Coss Coss eff. Parameter Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance Min. 7.5 --- --- --- --- --- --- --- --- --- --- --- --- --- Typ. --- --- --- --- 20 53 43 42 1900 290 12 2615 76 84 Max. Units Conditions --- S VDS = 50V, ID = 7.8A 64 ID = 13A 17 nC VDS = 400V 26 VGS = 10V, See Fig. 6 and 13 --- VDD = 250V --- ID = 13A ns --- RG = 8.8 --- RD = 21,See Fig. 10 --- VGS = 0V --- VDS = 25V --- pF = 1.0MHz, See Fig. 5 --- VGS = 0V, V DS = 1.0V, = 1.0MHz --- VGS = 0V, VDS = 400V, = 1.0MHz --- VGS = 0V, VDS = 0V to 400V
Avalanche Characteristics
Parameter
EAS IAR EAR Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy
Typ.
--- --- ---
Max.
430 13 18
Units
mJ A mJ
Thermal Resistance
Parameter
RJC RJA Junction-to-Case Junction-to-Ambient (PCB Mounted,steady-state)
Typ.
--- ---
Max.
0.70 40
Units
C/W
Diode Characteristics
IS
ISM
VSD trr Qrr ton
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol 13 --- --- showing the A G integral reverse --- --- 52 S p-n junction diode. --- --- 2.0 V TJ = 25C, IS = 13A, VGS = 0V --- 540 810 ns TJ = 25C, IF = 13A --- 4.1 6.1 C di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRFBL12N50A
100
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
100
I D , Drain-to-Source Current (A)
10
I D , Drain-to-Source Current (A)
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
10
1
4.5V
20s PULSE WIDTH TJ = 25 C
1 10 100
4.5V
20s PULSE WIDTH TJ = 150 C
1 10 100
0.1 0.1
1
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
3.0
ID = 13A
RDS(on) , Drain-to-Source On Resistance (Normalized)
I D , Drain-to-Source Current (A)
2.5
TJ = 150 C
10
2.0
TJ = 25 C
1
1.5
1.0
0.5
0.1 4.0
V DS = 50V 20s PULSE WIDTH 5.0 6.0 7.0 8.0
0.0 -60 -40 -20
VGS = 10V
0 20 40 60 80 100 120 140 160
VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature ( C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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IRFBL12N50A
100000 VGS = 0V, f = 1 MHZ Ciss = C + Cgd, C gs ds SHORTED Crss = C gd Coss = C + Cgd ds 20
ID = 13A VDS = 400V VDS = 250V VDS = 100V
10000
VGS , Gate-to-Source Voltage (V)
16
C, Capacitance(pF)
Ciss
1000
12
Coss
100
8
10
Crss
4
1 1 10 100 1000 0 0 10 20 30
FOR TEST CIRCUIT SEE FIGURE 13
40 50 60
VDS, Drain-to-Source Voltage (V)
QG , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
100
1000
I SD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY RDS(on)
100 10us 100us 1ms 1 10ms
T J = 150C
10
I D , Drain Current (A)
V G S = 0V A
1.4
10
TJ = 25C
1 0.4 0.6 0.8 1.0
0.1
TC = 25 C TJ = 150 C Single Pulse
10 100 1000 10000
1.2
V S D , S ou rc e-to-D ra in Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRFBL12N50A
14
VDS
12
RD
VGS RG
D.U.T.
+
I D , Drain Current (A)
10
- VDD
8
10V
Pulse Width 1 s Duty Factor 0.1 %
6
4
Fig 10a. Switching Time Test Circuit
VDS 90%
2
0 25 50 75 100 125 150
TC , Case Temperature ( C)
10% VGS
td(on) tr t d(off) tf
Fig 9. Maximum Drain Current Vs. Case Temperature
Fig 10b. Switching Time Waveforms
1
D = 0.50
Thermal Response (Z thJC )
0.20 0.1 0.10 0.05 0.02 0.01
SINGLE PULSE (THERMAL RESPONSE)
P DM t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC
0.01
0.001 0.00001
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFBL12N50A
1 5V
1000
EAS , Single Pulse Avalanche Energy (mJ)
TOP
800
VDS
L
D R IV E R
BOTTOM
ID 5.8A 8.2A 13A
RG
20V tp
D .U .T
IA S
+ V - DD
600
A
0 .0 1
400
Fig 12a. Unclamped Inductive Test Circuit
V (B R )D SS tp
200
0 25 50 75 100 125 150
Starting TJ , Junction Temperature ( C)
IAS
Fig 12b. Unclamped Inductive Waveforms
QG
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
10 V
QGS VG QGD
V D S av , A valanche V oltage (V )
660
640
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator Same Type as D.U.T.
620
50K 12V .2F .3F
600
D.U.T. VGS
3mA
+ V - DS
580 0 2 4 6 8 10 12 14
A
I av , A v alanc he C urrent (A)
IG ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
Fig 12d. Typical Drain-to-Source Voltage Vs. Avalanche Current
6
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IRFBL12N50A
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFET(R) Power MOSFETs
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7
IRFBL12N50A
Super-D2PakTM Package Outline
Dimensions are shown in millimeters (inches)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11)
Pulse width 300s; duty cycle 2%.
Starting TJ = 25C, L = 5.1mH
RG = 25, IAS = 13A. (See Figure 12)
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105 IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020 IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: (905) 453 2200 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111 IR JAPAN: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086 IR SOUTHEAST ASIA: 1 Kim Seng Promenade, Great World City West Tower, 13-11, Singapore 237994 Tel: ++ 65 838 4630 IR TAIWAN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 10673, Taiwan Tel: 886-2-2377-9936 Data and specifications subject to change without notice. 2/00
8
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